1. Field of the Invention
The present invention relates to memory architecture and access protocol for processor-oriented systems and more particularly, to pseudo-concurrency between a volatile memory and a non-volatile memory on a same data bus.
2. Description of the Related Art
Memory has long been an essential component of computing systems. Transfer rates provided by memory do not always keep up with system requirements for high-performance computing systems. In an effort to accommodate the increasing speeds of processors of high-performance computing systems, various levels of memory hierarchies are typically provided. As an example, near a high-speed processor of a computing system, a small amount of fast memory is usually provided. Downstream of fast memory, a larger and slower memory has been provided. It is not unusual for a computing system capable of high processor speeds to support multiple levels of cache memory and multiple levels of main memory. These memory levels are commonly populated by different types of memories.
A memory may generally be classified as either a volatile memory or a non-volatile memory. An example of a volatile memory is dynamic random access memory (DRAM), and an example of non-volatile memory is read only memory (ROM) or flash memory. Volatile memory and non-volatile memory have served different needs within a computing system. While the contents of a volatile memory are stored until power is turned off to a computing system, a non-volatile memory maintains its contents when power is turned off to a computing system. Volatile memory has generally been capable of greater memory speeds than non-volatile memory. Volatile memory and non-volatile memory, thus, commonly occupy different memory levels in a memory hierarchy.
For high-performance processor-oriented systems providing volatile memory and non-volatile memory, non-volatile memory and volatile memory have traditionally been supported on separate data buses. Typically, the volatile memory is coupled to a relatively fast data bus, and the non-volatile memory is coupled to a relatively slow data bus downstream of the relatively fast data bus. By providing a non-volatile memory and volatile memory on separate data buses, the data cycle of the non-volatile memory and the data cycle of the volatile memory are independent of each other. In this way, the data cycle of the non-volatile memory may be concurrent with the data cycle of the volatile memory.
A drawback of this memory architecture, however, has been relegating non-volatile memory to a relatively slow bus of a system. This architectural. constraint is particularly significant in a microcontroller environment. While in a computer system environment, most memory accesses are to a volatile memory, in a microcontroller environment, a significant number of memory accesses are to a non-volatile memory. In a computer system environment, code initially stored in a non-volatile memory is typically copied to a volatile memory and executed out of the volatile memory. In a microcontroller environment, however, code (e.g., eXecute-In-Place or XIP code) stored in a non-volatile memory is typically executed out of the non-volatile memory given the small amount of volatile memory available. Memory accesses to a volatile memory are undesirably slowed by the relatively slow speed of the bus supporting the non-volatile memory. Yet, in order to avoid bus latency attendant with supporting a volatile memory and non-volatile memory on a same data bus, many systems continue to provide the volatile memory on the relatively slow bus that supports the non-volatile memory.
For systems providing volatile memory and non-volatile memory on a same data bus, it is understood that during an access to either memory device, the other memory device generally must wait for completion of that access. This form of bus latency has long been perceived as a necessary cost of supporting volatile memory and non-volatile memory on a same data bus.
Briefly, a system and method according to the present invention operates a volatile memory and a non-volatile memory on a same data bus with pseudo-concurrency. Both the volatile memory and non-volatile memory share the data bus. Pseudo-concurrency is achieved by adjusting the timing of the address and control buses for the volatile memory and non-volatile memory so that data for the volatile memory and non-volatile memory are driven at the appropriate times.
In one disclosed embodiment, the volatile memory is further coupled to a first address bus, and the non-volatile memory is further coupled to a second address bus. The volatile memory may also be coupled to a first control bus, and the non-volatile memory may be coupled to a second control bus. The system may comprise a bus master coupled to the data bus, the first address bus, and the second address bus. The bus master may execute an access cycle to the volatile memory and concurrently precharge the non-volatile memory. The bus master may execute a data cycle to the non-volatile memory after executing an access cycle to the volatile memory. The bus master may also execute an access cycle to the non-volatile memory and concurrently precharge the volatile memory. The bus master may execute a data cycle to the volatile memory after executing an access cycle to the non-volatile memory.
In another disclosed embodiment, a volatile memory and a non-volatile memory are coupled to a multiplexed address bus. The system may comprise a bus master coupled to the data bus and multiplexed address bus. The bus master may execute an access cycle to the volatile memory and concurrently precharge the non-volatile memory. The bus master may execute a data cycle to the non-volatile memory after executing an access cycle to the volatile memory. The bus master may also execute an access cycle to the non-volatile memory and concurrently precharge the volatile memory. The bus master may execute a data cycle to the volatile memory after executing an access cycle to the non-volatile memory.
In accordance with the present invention, a non-volatile memory may be supported by a relatively fast bus, as opposed to a relatively slow bus. Further, the non-volatile memory and volatile memory may share signal pins coupled to the data bus, permitting a reduction in the number of signal pins for the system.